This is as.info, produced by makeinfo version 4.0 from as.texinfo.

START-INFO-DIR-ENTRY
* As: (as).                     The GNU assembler.
END-INFO-DIR-ENTRY

   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free
Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
     under the terms of the GNU Free Documentation License, Version 1.1
     or any later version published by the Free Software Foundation;
   with no Invariant Sections, with no Front-Cover Texts, and with no
    Back-Cover Texts.  A copy of the license is included in the
section entitled "GNU Free Documentation License".


File: as.info,  Node: Opcodes for i960,  Prev: Directives-i960,  Up: i960-Dependent

i960 Opcodes
------------

   All Intel 960 machine instructions are supported; *note i960
Command-line Options: Options-i960. for a discussion of selecting the
instruction subset for a particular 960 architecture.

   Some opcodes are processed beyond simply emitting a single
corresponding instruction: `callj', and Compare-and-Branch or
Compare-and-Jump instructions with target displacements larger than 13
bits.

* Menu:

* callj-i960::                  `callj'
* Compare-and-branch-i960::     Compare-and-Branch


File: as.info,  Node: callj-i960,  Next: Compare-and-branch-i960,  Up: Opcodes for i960

`callj'
.......

   You can write `callj' to have the assembler or the linker determine
the most appropriate form of subroutine call: `call', `bal', or
`calls'.  If the assembly source contains enough information--a
`.leafproc' or `.sysproc' directive defining the operand--then `as'
translates the `callj'; if not, it simply emits the `callj', leaving it
for the linker to resolve.


File: as.info,  Node: Compare-and-branch-i960,  Prev: callj-i960,  Up: Opcodes for i960

Compare-and-Branch
..................

   The 960 architectures provide combined Compare-and-Branch
instructions that permit you to store the branch target in the lower 13
bits of the instruction word itself.  However, if you specify a branch
target far enough away that its address won't fit in 13 bits, the
assembler can either issue an error, or convert your Compare-and-Branch
instruction into separate instructions to do the compare and the branch.

   Whether `as' gives an error or expands the instruction depends on
two choices you can make: whether you use the `-no-relax' option, and
whether you use a "Compare and Branch" instruction or a "Compare and
Jump" instruction.  The "Jump" instructions are _always_ expanded if
necessary; the "Branch" instructions are expanded when necessary
_unless_ you specify `-no-relax'--in which case `as' gives an error
instead.

   These are the Compare-and-Branch instructions, their "Jump" variants,
and the instruction pairs they may expand into:

             Compare and
          Branch      Jump       Expanded to
          ------    ------       ------------
             bbc                 chkbit; bno
             bbs                 chkbit; bo
          cmpibe    cmpije       cmpi; be
          cmpibg    cmpijg       cmpi; bg
         cmpibge   cmpijge       cmpi; bge
          cmpibl    cmpijl       cmpi; bl
         cmpible   cmpijle       cmpi; ble
         cmpibno   cmpijno       cmpi; bno
         cmpibne   cmpijne       cmpi; bne
          cmpibo    cmpijo       cmpi; bo
          cmpobe    cmpoje       cmpo; be
          cmpobg    cmpojg       cmpo; bg
         cmpobge   cmpojge       cmpo; bge
          cmpobl    cmpojl       cmpo; bl
         cmpoble   cmpojle       cmpo; ble
         cmpobne   cmpojne       cmpo; bne


File: as.info,  Node: M32R-Dependent,  Next: M68K-Dependent,  Prev: i960-Dependent,  Up: Machine Dependencies

M32R Dependent Features
=======================

* Menu:

* M32R-Opts::                   M32R Options
* M32R-Warnings::               M32R Warnings


File: as.info,  Node: M32R-Opts,  Next: M32R-Warnings,  Up: M32R-Dependent

M32R Options
------------

   The Mitsubishi M32R version of `as' has a few machine dependent
options:

`-m32rx'
     `as' can assemble code for several different members of the
     Mitsubishi M32R family.  Normally the default is to assemble code
     for the M32R microprocessor.  This option may be used to change
     the default to the M32RX microprocessor, which adds some more
     instructions to the basic M32R instruction set, and some
     additional parameters to some of the original instructions.

`-m32r'
     This option can be used to restore the assembler's default
     behaviour of assembling for the M32R microprocessor.  This can be
     useful if the default has been changed by a previous command line
     option.

`-warn-explicit-parallel-conflicts'
     Instructs `as' to produce warning messages when questionable
     parallel instructions are encountered.  This option is enabled by
     default, but `gcc' disables it when it invokes `as' directly.
     Questionable instructions are those whoes behaviour would be
     different if they were executed sequentially.  For example the
     code fragment `mv r1, r2 || mv r3, r1' produces a different result
     from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
     and then r2 into r1, whereas the later moves r2 into r1 and r3.

`-Wp'
     This is a shorter synonym for the
     _-warn-explicit-parallel-conflicts_ option.

`-no-warn-explicit-parallel-conflicts'
     Instructs `as' not to produce warning messages when questionable
     parallel instructions are encountered.

`-Wnp'
     This is a shorter synonym for the
     _-no-warn-explicit-parallel-conflicts_ option.


File: as.info,  Node: M32R-Warnings,  Prev: M32R-Opts,  Up: M32R-Dependent

M32R Warnings
-------------

   There are several warning and error messages that can be produced by
`as' which are specific to the M32R:

`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
     This message is only produced if warnings for explicit parallel
     conflicts have been enabled.  It indicates that the assembler has
     encountered a parallel instruction in which the destination
     register of the left hand instruction is used as an input register
     in the right hand instruction.  For example in this code fragment
     `mv r1, r2 || neg r3, r1' register r1 is the destination of the
     move instruction and the input to the neg instruction.

`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
     This message is only produced if warnings for explicit parallel
     conflicts have been enabled.  It indicates that the assembler has
     encountered a parallel instruction in which the destination
     register of the right hand instruction is used as an input
     register in the left hand instruction.  For example in this code
     fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
     of the neg instruction and the input to the move instruction.

`instruction `...' is for the M32RX only'
     This message is produced when the assembler encounters an
     instruction which is only supported by the M32Rx processor, and
     the `-m32rx' command line flag has not been specified to allow
     assembly of such instructions.

`unknown instruction `...''
     This message is produced when the assembler encounters an
     instruction which it doe snot recognise.

`only the NOP instruction can be issued in parallel on the m32r'
     This message is produced when the assembler encounters a parallel
     instruction which does not involve a NOP instruction and the
     `-m32rx' command line flag has not been specified.  Only the M32Rx
     processor is able to execute two instructions in parallel.

`instruction `...' cannot be executed in parallel.'
     This message is produced when the assembler encounters a parallel
     instruction which is made up of one or two instructions which
     cannot be executed in parallel.

`Instructions share the same execution pipeline'
     This message is produced when the assembler encounters a parallel
     instruction whoes components both use the same execution pipeline.

`Instructions write to the same destination register.'
     This message is produced when the assembler encounters a parallel
     instruction where both components attempt to modify the same
     register.  For example these code fragments will produce this
     message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
     @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
     r3, r4' (Both write to the condition bit)


File: as.info,  Node: M68K-Dependent,  Next: M68HC11-Dependent,  Prev: M32R-Dependent,  Up: Machine Dependencies

M680x0 Dependent Features
=========================

* Menu:

* M68K-Opts::                   M680x0 Options
* M68K-Syntax::                 Syntax
* M68K-Moto-Syntax::            Motorola Syntax
* M68K-Float::                  Floating Point
* M68K-Directives::             680x0 Machine Directives
* M68K-opcodes::                Opcodes


File: as.info,  Node: M68K-Opts,  Next: M68K-Syntax,  Up: M68K-Dependent

M680x0 Options
--------------

   The Motorola 680x0 version of `as' has a few machine dependent
options:

`-l'
     You can use the `-l' option to shorten the size of references to
     undefined symbols.  If you do not use the `-l' option, references
     to undefined symbols are wide enough for a full `long' (32 bits).
     (Since `as' cannot know where these symbols end up, `as' can only
     allocate space for the linker to fill in later.  Since `as' does
     not know how far away these symbols are, it allocates as much
     space as it can.)  If you use this option, the references are only
     one word wide (16 bits).  This may be useful if you want the
     object file to be as small as possible, and you know that the
     relevant symbols are always less than 17 bits away.

`--register-prefix-optional'
     For some configurations, especially those where the compiler
     normally does not prepend an underscore to the names of user
     variables, the assembler requires a `%' before any use of a
     register name.  This is intended to let the assembler distinguish
     between C variables and functions named `a0' through `a7', and so
     on.  The `%' is always accepted, but is not required for certain
     configurations, notably `sun3'.  The `--register-prefix-optional'
     option may be used to permit omitting the `%' even for
     configurations for which it is normally required.  If this is
     done, it will generally be impossible to refer to C variables and
     functions with the same names as register names.

`--bitwise-or'
     Normally the character `|' is treated as a comment character, which
     means that it can not be used in expressions.  The `--bitwise-or'
     option turns `|' into a normal character.  In this mode, you must
     either use C style comments, or start comments with a `#' character
     at the beginning of a line.

`--base-size-default-16  --base-size-default-32'
     If you use an addressing mode with a base register without
     specifying the size, `as' will normally use the full 32 bit value.
     For example, the addressing mode `%a0@(%d0)' is equivalent to
     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
     tell `as' to default to using the 16 bit value.  In this case,
     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
     `--base-size-default-32' option to restore the default behaviour.

`--disp-size-default-16  --disp-size-default-32'
     If you use an addressing mode with a displacement, and the value
     of the displacement is not known, `as' will normally assume that
     the value is 32 bits.  For example, if the symbol `disp' has not
     been defined, `as' will assemble the addressing mode
     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
     the `--disp-size-default-16' option to tell `as' to instead assume
     that the displacement is 16 bits.  In this case, `as' will
     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
     may use the `--disp-size-default-32' option to restore the default
     behaviour.

`--pcrel'
     Always keep branches PC-relative.  In the M680x0 architecture all
     branches are defined as PC-relative.  However, on some processors
     they are limited to word displacements maximum.  When `as' needs a
     long branch that is not available, it normally emits an absolute
     jump instead.  This option disables this substitution.  When this
     option is given and no long branches are available, only word
     branches will be emitted.  An error message will be generated if a
     word branch cannot reach its target.  This option has no effect on
     68020 and other processors that have long branches.  *note Branch
     Improvement: M68K-Branch..

`-m68000'
     `as' can assemble code for several different members of the
     Motorola 680x0 family.  The default depends upon how `as' was
     configured when it was built; normally, the default is to assemble
     code for the 68020 microprocessor.  The following options may be
     used to change the default.  These options control which
     instructions and addressing modes are permitted.  The members of
     the 680x0 family are very similar.  For detailed information about
     the differences, see the Motorola manuals.

    `-m68000'
    `-m68ec000'
    `-m68hc000'
    `-m68hc001'
    `-m68008'
    `-m68302'
    `-m68306'
    `-m68307'
    `-m68322'
    `-m68356'
          Assemble for the 68000. `-m68008', `-m68302', and so on are
          synonyms for `-m68000', since the chips are the same from the
          point of view of the assembler.

    `-m68010'
          Assemble for the 68010.

    `-m68020'
    `-m68ec020'
          Assemble for the 68020.  This is normally the default.

    `-m68030'
    `-m68ec030'
          Assemble for the 68030.

    `-m68040'
    `-m68ec040'
          Assemble for the 68040.

    `-m68060'
    `-m68ec060'
          Assemble for the 68060.

    `-mcpu32'
    `-m68330'
    `-m68331'
    `-m68332'
    `-m68333'
    `-m68334'
    `-m68336'
    `-m68340'
    `-m68341'
    `-m68349'
    `-m68360'
          Assemble for the CPU32 family of chips.

    `-m5200'
          Assemble for the ColdFire family of chips.

    `-m68881'
    `-m68882'
          Assemble 68881 floating point instructions.  This is the
          default for the 68020, 68030, and the CPU32.  The 68040 and
          68060 always support floating point instructions.

    `-mno-68881'
          Do not assemble 68881 floating point instructions.  This is
          the default for 68000 and the 68010.  The 68040 and 68060
          always support floating point instructions, even if this
          option is used.

    `-m68851'
          Assemble 68851 MMU instructions.  This is the default for the
          68020, 68030, and 68060.  The 68040 accepts a somewhat
          different set of MMU instructions; `-m68851' and `-m68040'
          should not be used together.

    `-mno-68851'
          Do not assemble 68851 MMU instructions.  This is the default
          for the 68000, 68010, and the CPU32.  The 68040 accepts a
          somewhat different set of MMU instructions.


File: as.info,  Node: M68K-Syntax,  Next: M68K-Moto-Syntax,  Prev: M68K-Opts,  Up: M68K-Dependent

Syntax
------

   This syntax for the Motorola 680x0 was developed at MIT.

   The 680x0 version of `as' uses instructions names and syntax
compatible with the Sun assembler.  Intervening periods are ignored;
for example, `movl' is equivalent to `mov.l'.

   In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), a suppressed address register
(`%za0' through `%za7'), or it may be omitted entirely.  The use of
SIZE means one of `w' or `l', and it may be omitted, along with the
leading colon, unless a scale is also specified.  The use of SCALE
means one of `1', `2', `4', or `8', and it may always be omitted along
with the leading colon.

   The following addressing modes are understood:
"Immediate"
     `#NUMBER'

"Data Register"
     `%d0' through `%d7'

"Address Register"
     `%a0' through `%a7'
     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
     also known as `%fp', the Frame Pointer.

"Address Register Indirect"
     `%a0@' through `%a7@'

"Address Register Postincrement"
     `%a0@+' through `%a7@+'

"Address Register Predecrement"
     `%a0@-' through `%a7@-'

"Indirect Plus Offset"
     `APC@(NUMBER)'

"Index"
     `APC@(NUMBER,REGISTER:SIZE:SCALE)'

     The NUMBER may be omitted.

"Postindex"
     `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'

     The ONUMBER or the REGISTER, but not both, may be omitted.

"Preindex"
     `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'

     The NUMBER may be omitted.  Omitting the REGISTER produces the
     Postindex addressing mode.

"Absolute"
     `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.


File: as.info,  Node: M68K-Moto-Syntax,  Next: M68K-Float,  Prev: M68K-Syntax,  Up: M68K-Dependent

Motorola Syntax
---------------

   The standard Motorola syntax for this chip differs from the syntax
already discussed (*note Syntax: M68K-Syntax.).  `as' can accept
Motorola syntax for operands, even if MIT syntax is used for other
operands in the same instruction.  The two kinds of syntax are fully
compatible.

   In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), or a suppressed address
register (`%za0' through `%za7').  The use of SIZE means one of `w' or
`l', and it may always be omitted along with the leading dot.  The use
of SCALE means one of `1', `2', `4', or `8', and it may always be
omitted along with the leading asterisk.

   The following additional addressing modes are understood:

"Address Register Indirect"
     `(%a0)' through `(%a7)'
     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
     also known as `%fp', the Frame Pointer.

"Address Register Postincrement"
     `(%a0)+' through `(%a7)+'

"Address Register Predecrement"
     `-(%a0)' through `-(%a7)'

"Indirect Plus Offset"
     `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.

     The NUMBER may also appear within the parentheses, as in
     `(NUMBER,%A0)'.  When used with the PC, the NUMBER may be omitted
     (with an address register, omitting the NUMBER produces Address
     Register Indirect mode).

"Index"
     `NUMBER(APC,REGISTER.SIZE*SCALE)'

     The NUMBER may be omitted, or it may appear within the
     parentheses.  The APC may be omitted.  The REGISTER and the APC
     may appear in either order.  If both APC and REGISTER are address
     registers, and the SIZE and SCALE are omitted, then the first
     register is taken as the base register, and the second as the
     index register.

"Postindex"
     `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'

     The ONUMBER, or the REGISTER, or both, may be omitted.  Either the
     NUMBER or the APC may be omitted, but not both.

"Preindex"
     `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'

     The NUMBER, or the APC, or the REGISTER, or any two of them, may
     be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC
     may appear in either order.  If both APC and REGISTER are address
     registers, and the SIZE and SCALE are omitted, then the first
     register is taken as the base register, and the second as the
     index register.


File: as.info,  Node: M68K-Float,  Next: M68K-Directives,  Prev: M68K-Moto-Syntax,  Up: M68K-Dependent

Floating Point
--------------

   Packed decimal (P) format floating literals are not supported.  Feel
free to add the code!

   The floating point formats generated by directives are these.

`.float'
     `Single' precision floating point constants.

`.double'
     `Double' precision floating point constants.

`.extend'
`.ldouble'
     `Extended' precision (`long double') floating point constants.


File: as.info,  Node: M68K-Directives,  Next: M68K-opcodes,  Prev: M68K-Float,  Up: M68K-Dependent

680x0 Machine Directives
------------------------

   In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.

`.data1'
     This directive is identical to a `.data 1' directive.

`.data2'
     This directive is identical to a `.data 2' directive.

`.even'
     This directive is a special case of the `.align' directive; it
     aligns the output to an even byte boundary.

`.skip'
     This directive is identical to a `.space' directive.


File: as.info,  Node: M68K-opcodes,  Prev: M68K-Directives,  Up: M68K-Dependent

Opcodes
-------

* Menu:

* M68K-Branch::                 Branch Improvement
* M68K-Chars::                  Special Characters


File: as.info,  Node: M68K-Branch,  Next: M68K-Chars,  Up: M68K-opcodes

Branch Improvement
..................

   Certain pseudo opcodes are permitted for branch instructions.  They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by substituting `j' for `b' at the
start of a Motorola mnemonic.

   The following table summarizes the pseudo-operations.  A `*' flags
cases that are more fully described after the table:

               Displacement
               +------------------------------------------------------------
               |                68020           68000/10, not PC-relative OK
     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
               +------------------------------------------------------------
          jbsr |bsrs    bsrw    bsrl            jsr
           jra |bras    braw    bral            jmp
     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
          fjXX | N/A    fbXXw   fbXXl            N/A
     
     XX: condition
     NX: negative of condition XX

                    `*'--see full description below

         `**'--this expansion mode is disallowed by `--pcrel'

`jbsr'
`jra'
     These are the simplest jump pseudo-operations; they always map to
     one particular machine instruction, depending on the displacement
     to the branch target.  This instruction will be a byte or word
     branch is that is sufficient.  Otherwise, a long branch will be
     emitted if available.  If no long branches are available and the
     `--pcrel' option is not given, an absolute long jump will be
     emitted instead.  If no long branches are available, the `--pcrel'
     option is given, and a word branch cannot reach the target, an
     error message is generated.

     In addition to standard branch operands, `as' allows these
     pseudo-operations to have all operands that are allowed for jsr
     and jmp, substituting these instructions if the operand given is
     not valid for a branch instruction.

`jXX'
     Here, `jXX' stands for an entire family of pseudo-operations,
     where XX is a conditional branch or condition-code test.  The full
     list of pseudo-ops in this family is:
           jhi   jls   jcc   jcs   jne   jeq   jvc
           jvs   jpl   jmi   jge   jlt   jgt   jle

     Usually, each of these pseudo-operations expands to a single branch
     instruction.  However, if a word branch is not sufficient, no long
     branches are available, and the `--pcrel' option is not given, `as'
     issues a longer code fragment in terms of NX, the opposite
     condition to XX.  For example, under these conditions:
              jXX foo
     gives
               bNXs oof
               jmp foo
           oof:

`dbXX'
     The full family of pseudo-operations covered here is
           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
           dbf    dbra   dbt

     Motorola `dbXX' instructions allow word displacements only.  When
     a word displacement is sufficient, each of these pseudo-operations
     expands to the corresponding Motorola instruction.  When a word
     displacement is not sufficient and long branches are available,
     when the source reads `dbXX foo', `as' emits
               dbXX oo1
               bras oo2
           oo1:bral foo
           oo2:

     If, however, long branches are not available and the `--pcrel'
     option is not given, `as' emits
               dbXX oo1
               bras oo2
           oo1:jmp foo
           oo2:

`fjXX'
     This family includes
           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
           fjugt  fjule  fjult  fjun

     Each of these pseudo-operations always expands to a single Motorola
     coprocessor branch instruction, word or long.  All Motorola
     coprocessor branch instructions allow both word and long
     displacements.


File: as.info,  Node: M68K-Chars,  Prev: M68K-Branch,  Up: M68K-opcodes

Special Characters
..................

   The immediate character is `#' for Sun compatibility.  The
line-comment character is `|' (unless the `--bitwise-or' option is
used).  If a `#' appears at the beginning of a line, it is treated as a
comment unless it looks like `# line file', in which case it is treated
normally.


File: as.info,  Node: M68HC11-Dependent,  Next: MIPS-Dependent,  Prev: M68K-Dependent,  Up: Machine Dependencies

M68HC11 and M68HC12 Dependent Features
======================================

* Menu:

* M68HC11-Opts::                   M68HC11 and M68HC12 Options
* M68HC11-Syntax::                 Syntax
* M68HC11-Float::                  Floating Point
* M68HC11-opcodes::                Opcodes


File: as.info,  Node: M68HC11-Opts,  Next: M68HC11-Syntax,  Up: M68HC11-Dependent

M68HC11 and M68HC12 Options
---------------------------

   The Motorola 68HC11 and 68HC12 version of `as' has a few machine
dependent options.

   This option switches the assembler in the M68HC11 mode. In this mode,
the assembler only accepts 68HC11 operands and mnemonics. It produces
code for the 68HC11.

   This option switches the assembler in the M68HC12 mode. In this mode,
the assembler also accepts 68HC12 operands and mnemonics. It produces
code for the 68HC12. A fiew 68HC11 instructions are replaced by some
68HC12 instructions as recommended by Motorola specifications.

   You can use the `--strict-direct-mode' option to disable the
automatic translation of direct page mode addressing into extended mode
when the instruction does not support direct mode.  For example, the
`clr' instruction does not support direct page mode addressing. When it
is used with the direct page mode, `as' will ignore it and generate an
absolute addressing.  This option prevents `as' from doing this, and
the wrong usage of the direct page mode will raise an error.

   The `--short-branchs' option turns off the translation of relative
branches into absolute branches when the branch offset is out of range.
By default `as' transforms the relative branch (`bsr', `bgt', `bge',
`beq', `bne', `ble', `blt', `bhi', `bcc', `bls', `bcs', `bmi', `bvs',
`bvs', `bra') into an absolute branch when the offset is out of the
-128 .. 127 range.  In that case, the `bsr' instruction is translated
into a `jsr', the `bra' instruction is translated into a `jmp' and the
conditional branchs instructions are inverted and followed by a `jmp'.
This option disables these translations and `as' will generate an error
if a relative branch is out of range. This option does not affect the
optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

   The `--force-long-branchs' option forces the translation of relative
branches into absolute branches. This option does not affect the
optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

   You can use the `--print-insn-syntax' option to obtain the syntax
description of the instruction when an error is detected.

   The `--print-opcodes' option prints the list of all the instructions
with their syntax. The first item of each line represents the
instruction name and the rest of the line indicates the possible
operands for that instruction. The list is printed in alphabetical
order. Once the list is printed `as' exits.

   The `--generate-example' option is similar to `--print-opcodes' but
it generates an example for each instruction instead.


File: as.info,  Node: M68HC11-Syntax,  Next: M68HC11-Float,  Prev: M68HC11-Opts,  Up: M68HC11-Dependent

Syntax
------

   In the M68HC11 syntax, the instruction name comes first and it may
be followed by one or several operands (up to three). Operands are
separated by comma (`,'). In the normal mode, `as' will complain if too
many operands are specified for a given instruction. In the MRI mode
(turned on with `-M' option), it will treat them as comments. Example:

     inx
     lda  #23
     bset 2,x #4
     brclr *bot #8 foo

   The following addressing modes are understood:
"Immediate"
     `#NUMBER'

"Address Register"
     `NUMBER,X', `NUMBER,Y'

     The NUMBER may be omitted in which case 0 is assumed.

"Direct Addressing mode"
     `*SYMBOL', or `*DIGITS'

"Absolute"
     `SYMBOL', or `DIGITS'


File: as.info,  Node: M68HC11-Float,  Next: M68HC11-opcodes,  Prev: M68HC11-Syntax,  Up: M68HC11-Dependent

Floating Point
--------------

   Packed decimal (P) format floating literals are not supported.  Feel
free to add the code!

   The floating point formats generated by directives are these.

`.float'
     `Single' precision floating point constants.

`.double'
     `Double' precision floating point constants.

`.extend'
`.ldouble'
     `Extended' precision (`long double') floating point constants.


File: as.info,  Node: M68HC11-opcodes,  Prev: M68HC11-Float,  Up: M68HC11-Dependent

Opcodes
-------

* Menu:

* M68HC11-Branch::                 Branch Improvement


File: as.info,  Node: M68HC11-Branch,  Up: M68HC11-opcodes

Branch Improvement
..................

   Certain pseudo opcodes are permitted for branch instructions.  They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by prepending `j' to the start of
Motorola mnemonic. These pseudo opcodes are not affected by the
`--short-branchs' or `--force-long-branchs' options.

   The following table summarizes the pseudo-operations.

                                   Displacement Width
               +-------------------------------------------------------------+
               |                     Options                                 |
               |    --short-branchs            --force-long-branchs          |
               +--------------------------+----------------------------------+
     Pseudo-Op |BYTE             WORD     | BYTE          WORD               |
               +--------------------------+----------------------------------+
           bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
           bra | bra <pc-rel>    <error>  |               jmp <abs>          |
          jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
          jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
           bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
          jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
               |                jmp <abs> |                                  |
               +--------------------------+----------------------------------+
     XX: condition
     NX: negative of condition XX

`jbsr'
`jbra'
     These are the simplest jump pseudo-operations; they always map to
     one particular machine instruction, depending on the displacement
     to the branch target.

`jbXX'
     Here, `jbXX' stands for an entire family of pseudo-operations,
     where XX is a conditional branch or condition-code test.  The full
     list of pseudo-ops in this family is:
           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi

     For the cases of non-PC relative displacements and long
     displacements, `as' issues a longer code fragment in terms of NX,
     the opposite condition to XX.  For example, for the non-PC
     relative case:
              jbXX foo
     gives
               bNXs oof
               jmp foo
           oof:


File: as.info,  Node: MIPS-Dependent,  Next: SH-Dependent,  Prev: M68HC11-Dependent,  Up: Machine Dependencies

MIPS Dependent Features
=======================

   GNU `as' for MIPS architectures supports several different MIPS
processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For
information about the MIPS instruction set, see `MIPS RISC
Architecture', by Kane and Heindrich (Prentice-Hall).  For an overview
of MIPS assembly conventions, see "Appendix D: Assembly Language
Programming" in the same work.

* Menu:

* MIPS Opts::   	Assembler options
* MIPS Object:: 	ECOFF object code
* MIPS Stabs::  	Directives for debugging information
* MIPS ISA::    	Directives to override the ISA level
* MIPS autoextend::	Directives for extending MIPS 16 bit instructions
* MIPS insn::		Directive to mark data as an instruction
* MIPS option stack::	Directives to save and restore options


File: as.info,  Node: MIPS Opts,  Next: MIPS Object,  Up: MIPS-Dependent

Assembler options
-----------------

   The MIPS configurations of GNU `as' support these special options:

`-G NUM'
     This option sets the largest size of an object that can be
     referenced implicitly with the `gp' register.  It is only accepted
     for targets that use ECOFF format.  The default value is 8.

`-EB'
`-EL'
     Any MIPS configuration of `as' can select big-endian or
     little-endian output at run time (unlike the other GNU development
     tools, which must be configured for one or the other).  Use `-EB'
     to select big-endian output, and `-EL' for little-endian.

`-mips1'
`-mips2'
`-mips3'
`-mips4'
`-mips5'
`-mips32'
`-mips64'
     Generate code for a particular MIPS Instruction Set Architecture
     level.  `-mips1' corresponds to the R2000 and R3000 processors,
     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
     `-mips32', and `-mips64' correspond to generic MIPS V, MIPS32, and
     MIPS64 ISA processors, respectively.  You can also switch
     instruction sets during the assembly; see *Note Directives to
     override the ISA level: MIPS ISA.

`-mgp32'
     Assume that 32-bit general purpose registers are available.  This
     affects synthetic instructions such as `move', which will assemble
     to a 32-bit or a 64-bit instruction depending on this flag.  On
     some MIPS variants there is a 32-bit mode flag; when this flag is
     set, 64-bit instructions generate a trap.  Also, some 32-bit OSes
     only save the 32-bit registers on a context switch, so it is
     essential never to use the 64-bit registers.

`-mgp64'
     Assume that 64-bit general purpose registers are available.  This
     is provided in the interests of symmetry with -gp32.

`-mips16'
`-no-mips16'
     Generate code for the MIPS 16 processor.  This is equivalent to
     putting `.set mips16' at the start of the assembly file.
     `-no-mips16' turns off this option.

`-mfix7000'
`-no-mfix7000'
     Cause nops to be inserted if the read of the destination register
     of an mfhi or mflo instruction occurs in the following two
     instructions.

`-m4010'
`-no-m4010'
     Generate code for the LSI R4010 chip.  This tells the assembler to
     accept the R4010 specific instructions (`addciu', `ffc', etc.),
     and to not schedule `nop' instructions around accesses to the `HI'
     and `LO' registers.  `-no-m4010' turns off this option.

`-m4650'
`-no-m4650'
     Generate code for the MIPS R4650 chip.  This tells the assembler
     to accept the `mad' and `madu' instruction, and to not schedule
     `nop' instructions around accesses to the `HI' and `LO' registers.
     `-no-m4650' turns off this option.

`-m3900'
`-no-m3900'
`-m4100'
`-no-m4100'
     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
     This tells the assembler to accept instructions specific to that
     chip, and to schedule for that chip's hazards.

`-mcpu=CPU'
     Generate code for a particular MIPS cpu.  It is exactly equivalent
     to `-mCPU', except that there are more value of CPU understood.
     Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600,
          4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, 6000,
          rm7000, 8000, 10000, mips32-4k, sb1

`-nocpp'
     This option is ignored.  It is accepted for command-line
     compatibility with other assemblers, which use it to turn off C
     style preprocessing.  With GNU `as', there is no need for
     `-nocpp', because the GNU assembler itself never runs the C
     preprocessor.

`--construct-floats'
`--no-construct-floats'
     The `--no-construct-floats' option disables the construction of
     double width floating point constants by loading the two halves of
     the value into the two single width floating point registers that
     make up the double width register.  This feature is useful if the
     processor support the FR bit in its status  register, and this bit
     is known (by the programmer) to be set.  This bit prevents the
     aliasing of the double width register by the single width
     registers.

     By default `--construct-floats' is selected, allowing construction
     of these floating point constants.

`--trap'
`--no-break'
     `as' automatically macro expands certain division and
     multiplication instructions to check for overflow and division by
     zero.  This option causes `as' to generate code to take a trap
     exception rather than a break exception when an error is detected.
     The trap instructions are only supported at Instruction Set
     Architecture level 2 and higher.

`--break'
`--no-trap'
     Generate code to take a break exception rather than a trap
     exception when an error is detected.  This is the default.


File: as.info,  Node: MIPS Object,  Next: MIPS Stabs,  Prev: MIPS Opts,  Up: MIPS-Dependent

MIPS ECOFF object code
----------------------

   Assembling for a MIPS ECOFF target supports some additional sections
besides the usual `.text', `.data' and `.bss'.  The additional sections
are `.rdata', used for read-only data, `.sdata', used for small data,
and `.sbss', used for small common objects.

   When assembling for ECOFF, the assembler uses the `$gp' (`$28')
register to form the address of a "small object".  Any object in the
`.sdata' or `.sbss' sections is considered "small" in this sense.  For
external objects, or for objects in the `.bss' section, you can use the
`gcc' `-G' option to control the size of objects addressed via `$gp';
the default value is 8, meaning that a reference to any object eight
bytes or smaller uses `$gp'.  Passing `-G 0' to `as' prevents it from
using the `$gp' register on the basis of object size (but the assembler
uses `$gp' for objects in `.sdata' or `sbss' in any case).  The size of
an object in the `.bss' section is set by the `.comm' or `.lcomm'
directive that defines it.  The size of an external object may be set
with the `.extern' directive.  For example, `.extern sym,4' declares
that the object at `sym' is 4 bytes in length, whie leaving `sym'
otherwise undefined.

   Using small ECOFF objects requires linker support, and assumes that
the `$gp' register is correctly initialized (normally done
automatically by the startup code).  MIPS ECOFF assembly code must not
modify the `$gp' register.


File: as.info,  Node: MIPS Stabs,  Next: MIPS ISA,  Prev: MIPS Object,  Up: MIPS-Dependent

Directives for debugging information
------------------------------------

   MIPS ECOFF `as' supports several directives used for generating
debugging information which are not support by traditional MIPS
assemblers.  These are `.def', `.endef', `.dim', `.file', `.scl',
`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
The debugging information generated by the three `.stab' directives can
only be read by GDB, not by traditional MIPS debuggers (this
enhancement is required to fully support C++ debugging).  These
directives are primarily used by compilers, not assembly language
programmers!


File: as.info,  Node: MIPS ISA,  Next: MIPS autoextend,  Prev: MIPS Stabs,  Up: MIPS-Dependent

Directives to override the ISA level
------------------------------------

   GNU `as' supports an additional directive to change the MIPS
Instruction Set Architecture level on the fly: `.set mipsN'.  N should
be a number from 0 to 5, or 32 or 64.  The values 1 to 5, 32, and 64
make the assembler accept instructions for the corresponding ISA level,
from that point on in the assembly.  `.set mipsN' affects not only
which instructions are permitted, but also how certain macros are
expanded.  `.set mips0' restores the ISA level to its original level:
either the level you selected with command line options, or the default
for your configuration.  You can use this feature to permit specific
R4000 instructions while assembling in 32 bit mode.  Use this directive
with care!

   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
which it will assemble instructions for the MIPS 16 processor.  Use
`.set nomips16' to return to normal 32 bit mode.

   Traditional MIPS assemblers do not support this directive.


File: as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS ISA,  Up: MIPS-Dependent

Directives for extending MIPS 16 bit instructions
-------------------------------------------------

   By default, MIPS 16 instructions are automatically extended to 32
bits when necessary.  The directive `.set noautoextend' will turn this
off.  When `.set noautoextend' is in effect, any 32 bit instruction
must be explicitly extended with the `.e' modifier (e.g., `li.e
$4,1000').  The directive `.set autoextend' may be used to once again
automatically extend instructions when necessary.

   This directive is only meaningful when in MIPS 16 mode.  Traditional
MIPS assemblers do not support this directive.


File: as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent

Directive to mark data as an instruction
----------------------------------------

   The `.insn' directive tells `as' that the following data is actually
instructions.  This makes a difference in MIPS 16 mode: when loading
the address of a label which precedes instructions, `as' automatically
adds 1 to the value, so that jumping to the loaded address will do the
right thing.


File: as.info,  Node: MIPS option stack,  Prev: MIPS insn,  Up: MIPS-Dependent

Directives to save and restore options
--------------------------------------

   The directives `.set push' and `.set pop' may be used to save and
restore the current settings for all the options which are controlled
by `.set'.  The `.set push' directive saves the current settings on a
stack.  The `.set pop' directive pops the stack and restores the
settings.

   These directives can be useful inside an macro which must change an
option such as the ISA level or instruction reordering but does not want
to change the state of the code which invoked the macro.

   Traditional MIPS assemblers do not support these directives.


File: as.info,  Node: PJ-Dependent,  Next: Sparc-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies

picoJava Dependent Features
===========================

* Menu:

* PJ Options::              Options


File: as.info,  Node: PJ Options,  Up: PJ-Dependent

Options
-------

   `as' has two addiitional command-line options for the picoJava
architecture.
`-ml'
     This option selects little endian data output.

`-mb'
     This option selects big endian data output.


File: as.info,  Node: SH-Dependent,  Next: PJ-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies

Hitachi SH Dependent Features
=============================

* Menu:

* SH Options::              Options
* SH Syntax::               Syntax
* SH Floating Point::       Floating Point
* SH Directives::           SH Machine Directives
* SH Opcodes::              Opcodes


File: as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent

Options
-------

   `as' has no additional command-line options for the Hitachi SH
family.


File: as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent

Syntax
------

* Menu:

* SH-Chars::                Special Characters
* SH-Regs::                 Register Names
* SH-Addressing::           Addressing Modes


File: as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.


File: as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax

Register Names
..............

   You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and
`r15' to refer to the SH registers.

   The SH also has these control registers:

`pr'
     procedure register (holds return address)

`pc'
     program counter

`mach'
`macl'
     high and low multiply accumulator registers

`sr'
     status register

`gbr'
     global base register

`vbr'
     vector base register (for interrupt vectors)


File: as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax

Addressing Modes
................

   `as' understands the following addressing modes for the SH.  `RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.

`RN'
     Register direct

`@RN'
     Register indirect

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@(DISP, RN)'
     Register indirect with displacement

`@(R0, RN)'
     Register indexed

`@(DISP, GBR)'
     `GBR' offset

`@(R0, GBR)'
     GBR indexed

`ADDR'
`@(DISP, PC)'
     PC relative address (for branch or for addressing memory).  The
     `as' implementation allows you to use the simpler form ADDR
     anywhere a PC relative address is called for; the alternate form
     is supported for compatibility with other assemblers.

`#IMM'
     Immediate data


File: as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent

Floating Point
--------------

   The SH family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.


File: as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent

SH Machine Directives
---------------------

`uaword'
`ualong'
     `as' will issue a warning when a misaligned `.word' or `.long'
     directive is used.  You may use `.uaword' or `.ualong' to indicate
     that the value is intentionally misaligned.

